Report Number: CSL-TR-97-737
Institution: Stanford University, Computer Systems Laboratory
Title: Stochastic Congestion Model for VLSI Systems
Author: Hung, Patrick
Author: Flynn, Michael J.
Date: october 1997
Abstract: Designing with deep submicron feature size presents new
challenges in complexity, performance, and productivity.
Information on routing congestion and interconnect area are
critical in the pre-RTL stage in order to forecast the whole
die size, define the timing specifications, and evaluate the
chip power consumption.
In this report, we propose a stochastic model for VLSI
interconnect routing, which can be used to estimate the
routing congestion and the interconnect area in the pre-RTL
stage. First, we define the uniform and geometric routing
distributions, and introduce a simple and efficient algorithm
to calculate the routing probabilities. We then derive the
routing probabilities among multiple functional blocks, and
investigate the effects of routing obstacles. Finally, we map
the chip to a Cartesian coordinate system, and model
routability based on the supply and demand distributions of