Report Number: CSL-TR-96-706
Institution: Stanford University, Computer Systems Laboratory
Title: Optimum Placement and Routing of Multiplier Partial Product
Author: Al-Twaijry, Hesham
Author: Flynn, Michael J.
Date: September 1996
Abstract: An algorithm that builds a multiplier under the constraint of
a limited number of wiring tracks is designed. The algorithm
has been implemented. The program is then used to compare
several designs of an IEEE floating point multiplier using
several delay models.