Report Number: CSL-TR-94-642
Institution: Stanford University, Computer Systems Laboratory
Title: An Apparatus for Pseudo-Deterministic Testing
Author: Mukund, Shridhar K.
Author: McCluskey, Edward J.
Author: Rao, T.R.N.
Date: October 1994
Abstract: Pseudo-random testing is popularly used, particularly in
Built-In Self Test (BIST) applications. To achieve a desired
fault coverage, pseudo-random patterns are often supplemented
with few deterministic patterns. When positions of
deterministic patterns in the pseudo-random sequence are
known a priori, pseudo-random sub-sequences can be chosen
such that they also cover these deterministic patterns. We
call this method of test application, pseudo-deterministic
testing. The theory of discrete logarithm has been applied to
determine positions of bit-patterns in the pseudo-random
sequence generated by a modular form or internal-XOR Line ar
Feedback Shift Register (LFSR) [5,7]. However, the scheme
requires that all the inputs of the combinational logic block
(CLB), under test, come from the same LFSR source. This
constraint in circuit configuration severely limits its
In this paper, we propose a practical and cost effective
technique for pseudo-de terministic testing. For most part,
the problem of circuit configuration has been simplified to
one of scan path insertion, by employing LFSR/SR (an
arbitrary length shift register driven by a standard form or
external-XOR LFSR). To enable the usage of LFSR/SR as a
pseudo-deterministic pattern source, we propose a method to
determine positions of bit-patterns, at arbitrarily chosen
tap configurations, in the LFSR/SR sequence.