Report Number: CSL-TR-93-577
Institution: Stanford University, Computer Systems Laboratory
Title: Implementation of a Three-Stage Banyan-Based Atchitecture
with Input and Output Buffers for Large Fast Packet Switches
Author: Chiussi, Fabio M.
Author: Tobagi, Fouad A.
Date: June 1993
Abstract: Fast packet switching, also referred to as Asynchronous
Transfer Mode (ATM), has emerged as the most appropriate
switching technique for future Broadband Integrated Services
Digital Networks (B-ISDN). A three-stage banyan-based switch
architecture with input and output buffers has been recently
described [Chi93]. Such architecture, also referred to as the
Memory/Space/Memory (MSM) switching fabric, is capable of
meeting the challenges posed by a successful deployment of
B-ISDN; namely, it is made nonblocking with low complexity,
and is scalable to large sizes (>1000 input/output ports); it
supports a wide diversity of traffic patterns, including
highly-bursty traffic; it maintains packet sequence, is
self-routing, and is simple to operate.