BIB-VERSION:: CS-TR-v2.0
          ID:: STAN//CSL-TR-99-786
       ENTRY:: November 12, 1999 
ORGANIZATION:: Stanford University, Computer Systems Laboratory
       TITLE:: High-Speed Interconnect Schemes for a Pipelined FPGA 
        TYPE:: Technical Report
      AUTHOR:: Lee, Hyuk-Jun
      AUTHOR:: Flynn, Michael J. 
        DATE:: August 1999
       PAGES:: 24
    ABSTRACT:: This paper presents two high-speed interconnect
schemes for a pipelined FPGA utilizing a locally synchronized
postcharging technique.  By avoiding a global synchronized
clock, we reduce the power consumption significantly.  Through
postcharging the interconnect and overlapping the postcharging
delay with the logic delay, we successfully hide the
postcharge time.  The long channel devices reduce the area penalty
due to delay elements significantly.  The timing simulation is
done using Hspice for a TSMC 0.35 um and area
is measured by drawing key elements in MAGIC and using the area
model developed in [2]. The postcharge scheme shows a 30% delay
reduction over the precharge scheme and up to 310% and 230%
delay reductions over the conventiaonal NMOS pass transistor
scheme and the tri-state buffer scheme.
         END:: STAN//CSL-TR-99-786