BIB-VERSION:: CS-TR-v2.0
          ID:: STAN//CSL-TR-99-783
       ENTRY:: November 29, 1999
ORGANIZATION:: Stanford University, Computer Systems Laboratory
       TITLE:: Optimum Instruction-level Parallelism (ILP) for Superscalar
               and VLIW Processors
        TYPE:: Technical Report
      AUTHOR:: Hung, Patrick
      AUTHOR:: Flynn, Michael J.
        DATE:: July 1999
       PAGES:: 13
    ABSTRACT:: Modern superscalar and VLIW processors fetch, decode,
               issue, execute, and retire multiple instructions per
               cycle.  By taking advantage of instruction-level
               parallelism (ILP), processor performance can be
               improved substantially.  However, increasing the level 
               of ILP may eventually result in diminishing and
               negative returns due to control and data dependencies
               among subsequent instructions as well as resource 
               conflicts within a processor.  Moreover, the 
               additional ILP complexity can have significant 
               overload in cycle time and latency. 
               This technical report uses a generic processor
               model to investigate the optimum level of ILP
               for superscalar and VLIW processors.
      NOTES:: [Adminitrivia V1/Prg/19991129]
         END:: STAN//CSL-TR-99-783