BIB-VERSION:: CS-TR-v2.0
          ID:: STAN//CSL-TR-99-780
       ENTRY:: April 19, 1999 
ORGANIZATION:: Stanford University, Computer Systems Laboratory
       TITLE:: Coarse Grain Carry Architecture for FPGA
        TYPE:: Technical Report
      AUTHOR:: Lee, Hyuk-Jun
      AUTHOR:: Flynn, Michael 
        DATE:: February 1999
       PAGES:: 37
    ABSTRACT:: In this report we investigated several methods to improve
               the performance of FPGA for general purpose computing.
               In the early stage of this research we identified the fine
               grain size of current FPGA as the major performance 
               bottleneck.  To increase the grain size, we introduced 
               coarse grain carry architecture that can increase the
               granularity of arithmetic operations including addition
               and multiplication.  We used throughput density as a
               cost/performance metric to justify the benefit of the new
               architecture.  We could achieve roughly up to 5 times larger
               throughput density for selected applications.  Along with that
               we also introduced a dual-rail carry structure to improve
               the performance of a carry chain, which usually set the cycle
               time of a FPGA design.  A carry select adder built from the 
               dual-rail carry structure reduces the carry chain delay by
               a factor of two.
        END:: STAN//CSL-TR-99-780