BIB-VERSION:: CS-TR-v2.0
          ID:: STAN//CSL-TR-97-748
       ENTRY:: January 21, 1998
ORGANIZATION:: Stanford University, Computer Systems Laboratory
       TITLE:: Decision Diagrams and Pass Transistor Logic Synthesis
        TYPE:: Technical Report
      AUTHOR:: Bertacco, V.
      AUTHOR:: Minato, S.
      AUTHOR:: Verplaetse, P.
      AUTHOR:: Benini, L.
      AUTHOR:: Micheli, and G. De
        DATE:: December 1997
       PAGES:: 12
    ABSTRACT:: Since the relative importance of interconnections increases
               as feature size decreases, standard-cell based synthesis
               becomes less effective when deep-submicron technologies
               become available. Intra-cell connectivity can be decreased by
               the use of macro-cells. In this work we present methods for
               the automatic generation of macro-cells using pass
               transistors and domino logic. The synthesis of these cells is
               based on BDD and ZBDD representations of the logic functions.
               We address specific problems associated with the BDD approach
               (level degradation, long paths) and the ZBDD approach (sneak
               paths, charge sharing, long paths). We compare performance of
               the macro-cells approach versus the conventional
               standard-cell approach based on accurate electrical
               simulation. This shows that the macro-cells perform well up
               to a certain complexity of the logic function. Functions of
               high complexity must be decomposed into smaller logic blocks
               that can directly be mapped to macro-cells.
       NOTES:: [Adminitrivia V1/Prg/19980121]
         END:: STAN//CSL-TR-97-748