BIB-VERSION:: CS-TR-v2.0
          ID:: STAN//CSL-TR-97-732
       ENTRY:: November 20, 1997
ORGANIZATION:: Stanford University, Computer Systems Laboratory
       TITLE:: Efficient Exception Handling Techniques for High-Performance
               Processor Architectures
        TYPE:: Technical Report
      AUTHOR:: Rudd, Kevin W.
        DATE:: October 1997
       PAGES:: 67
    ABSTRACT:: Providing precise exceptions has driven much of the
               complexity in modern processor designs. While this complexity
               is required to maintain the illusion of a processor based on
               a sequential architectural model, it also results in reduced
               performance during normal execution. The existing notion of
               precise exceptions is limited to processors based on a
               sequential architectural model and there have been few
               techniques developed that are applicable to processors that
               are not based on this model. Processors with exposed
               pipelines (typical of VLIW processors) do not conform to the
               sequential execution model. These processors have explicit
               overlaps in operation execution and thus cannot support the
               traditional notion of precise exceptions; most exception
               handling techniques for these processors require restrictive
               software scheduling. In this report, we generalize the notion
               of a precise exception and extend the applicability of
               precise exceptions to a wider range of architectures. We
               propose precise exception handling techniques that solve the
               problem of efficient exception handling for both sequential
               architectures as well as exposed pipeline architectures. We
               also show how these techniques can provide efficient support
               for speculative execution past multiple branches for both
               architectures as well as latency tolerance for exposed
               pipeline architectures.
       NOTES:: [Adminitrivia V1/Prg/19971120]
         END:: STAN//CSL-TR-97-732