BIB-VERSION:: CS-TR-v2.0
          ID:: STAN//CSL-TR-96-692
       ENTRY:: June 12, 1996
ORGANIZATION:: Stanford University, Computer Systems Laboratory
       TITLE:: Delay Balancing of Wave Pipelined Multiplier Counter Trees
               Using Pass Transistor Multiplexers
        TYPE:: Technical Report
      AUTHOR:: Kishigami, Hidechika
      AUTHOR:: Nowka, Kevin J.
      AUTHOR:: Flynn, Michael J.
        DATE:: January 1996
       PAGES:: 26
    ABSTRACT:: Wave pipelining is an attractive technique used in high-speed
               digital circuits to speed-up pipeline clock-rate by
               eliminating the synchronizing elements between pipeline
               stages.

               Wave-pipelining has been successfully applied to the design
               of CMOS multipliers which have demonstrated speed-ups of
               clock-rate 4 to 7 times over their non-pipelined design. In
               order to achieve high clock-rate by using wave-pipelining
               techniques, it is necessary to equalize (balance) all signal
               path delay of the circuit. In an earlier study a multiplier
               was designed by using only 2-inputs NAND gates and inverters
               as primitives in order to reduce delay variations of the
               circuit.

               Alternatively, there are several reports that use
               pass-transistor logic as primitives for multipliers to
               achieve very low latency. Pass-transistor logic seems
               attractive for reducing circuit delay variations.

               In this report we describe a design of wave-pipelined counter
               tree, which is a central part of parallel multiplier, and
               detail a method to balance the delay of (4,2) counter using
               pass-transistor multiplexers (PTMs) as primitives to achieve
               both higher clock-rate and smaller latency. Simulations of
               the wave-pipelined counter tree demonstrated 0.8ns clock-rate
               and 2.33ns latency through the use of pass-transistor
               multiplexers (PTMs) for a 0.8$\mu$m CMOS process. This data
               suggests that using pass-transistor multiplexers as primitives
               for wave-pipelined circuits is useful to achieve both higher
               clock-rate and lower latency.
       NOTES:: [Adminitrivia V1/Prg/19960612]
         END:: STAN//CSL-TR-96-692