BIB-VERSION:: CS-TR-v2.0
          ID:: STAN//CSL-TR-95-686
       ENTRY:: February 14, 1996
ORGANIZATION:: Stanford University, Computer Systems Laboratory
       TITLE:: Automatic Synthesis of Burst-Mode Asynchronous Controllers
        TYPE:: Thesis
        TYPE:: Technical Report
      AUTHOR:: Nowick, Steven Mark
        DATE:: December 1995
       PAGES:: 173
    ABSTRACT:: Asynchronous design has enjoyed a revival of interest
               recently, as designers seek to eliminate penalties of
               traditional synchronous design. In principle, asynchronous
               methods promise to avoid overhead due to clock skew,
               worst-case design assumptions and resynchronization of
               asynchronous external inputs. In practice, however, many
               asynchronous design methods suffer from a number of problems:
               unsound algorithms (implementations may have hazards), harsh
               restrictions on the range of designs that can be handled
               (single-input changes only), incompatibility with existing
               design styles and inefficiency in the resulting circuits.

               This thesis presents a new locally-clocked design method for
               the synthesis of asynchronous controllers. The method has
               been automated, is proven correct and produces
               high-performance implementations which are hazard-free at the
               gate-level. Implementations allow multiple-input changes and
               handle a relatively unconstrained class of behaviors (called
               "burst-mode" specifications). The method produces
               state-machine implementations with a minimal or near-minimal
               number of states. Implementations can be easily built in such
               common VLSI design styles as gate-array, standard cell and
               full-custom. Realizations typically have the latency of their
               combinational logic.

               A complete set of state and logic minimization algorithms has
               been developed and automated for the synthesis method. The
               logic minimization algorithm differs from existing algorithms
               since it generates two-level minimized logic which is also
               hazard-free.

               The synthesis program is used to produce competitive
               implementations for several published designs. In addition, a
               large real-world controller is designed as a case study: an
               asynchronous second-level cache controller for a new RISC
               processor.
       NOTES:: [Adminitrivia V1/Prg/19960214]
         END:: STAN//CSL-TR-95-686