BIB-VERSION:: CS-TR-v2.0
          ID:: STAN//CSL-TR-95-673
       ENTRY:: July 27, 1995
ORGANIZATION:: Stanford University, Computer Systems Laboratory
       TITLE:: Informing Loads: Enabling Software to Observe and React to
               Memory Behavior
        TYPE:: Technical Report
      AUTHOR:: Horowitz, Mark
      AUTHOR:: Martonosi, Margaret
      AUTHOR:: Mowry, Todd C.
      AUTHOR:: Smith, Michael D.
        DATE:: July 1995
       PAGES:: 23
    ABSTRACT:: Memory latency is an important bottleneck in system
               performance that cannot be adequately solved by hardware
               alone. Several promising software techniques have been shown
               to address this problem successfully in specific situations.
               However, the generality of these software approaches has been
               limited because current architectures do not provide a
               fine-grained, low-overhead mechanism to observe memory
               behavior directly. To fill this need, we propose a new set of
               memory operations called informing memory operations, and in
               particular, we describe the design and functionality of an
               informing load instruction. This instruction serves as a
               primitive that allows the software to observe cache misses
               and to act upon this information inexpensively (i.e. under
               the miss, when the processor would typically be idle) within
               the current software context.

               Informing loads enable new solutions to several important
               software problems. We demonstrate this through examples that
               show their usefulness in (i) the collection of fine-grained
               memory profiles with high precision and low overhead and (ii)
               the automatic improvement of memory system performance
               through compiler techniques that take advantage of cache-miss
               information. Overall, we find that the apparent benefit of
               an informing load instruction is quite high, while the
               hardware cost of this functionality is quite modest. In
               fact, the bulk of the required hardware support is already
               present in today's high-performance processors.
       NOTES:: [Adminitrivia V1/Prg/19950727]
         END:: STAN//CSL-TR-95-673