BIB-VERSION:: CS-TR-v2.0
          ID:: STAN//CSL-TR-95-672
       ENTRY:: June 28, 1995
ORGANIZATION:: Stanford University, Computer Systems Laboratory
       TITLE:: Delay Models for CMOS Circuits
        TYPE:: Technical Report
      AUTHOR:: McFarland, Grant
      AUTHOR:: Flynn, Michael
        DATE:: June 1995
       PAGES:: 31
    ABSTRACT:: Four different CMOS inverter delay models are derived and
               compared. It is shown that inverter delay can be estimated
               with fair accuracy over a wide range of input rise times and
               loads as the sum of two terms, one proportional to the input
               rise time, and one proportional to the capacitive load.
               Methods for estimating device capacitance from HSPICE
               parameters are presented, as well as means of including added
               delay due to wire resistance and the use of series
               transistors.
       NOTES:: [Adminitrivia V1/Prg/19950628]
         END:: STAN//CSL-TR-95-672