BIB-VERSION:: CS-TR-v2.0
          ID:: STAN//CSL-TR-95-669
       ENTRY:: June 28, 1995
ORGANIZATION:: Stanford University, Computer Systems Laboratory
       TITLE:: Testing BiCMOS and Dynamic CMOS Logic
        TYPE:: Thesis
        TYPE:: Technical Report
      AUTHOR:: Ma, Siyad
        DATE:: June 1995
       PAGES:: 55
    ABSTRACT:: In a normal integrated circuit (IC) production cycle,
               manufactured ICs are tested to remove defective parts. The
               purpose of this research is to study the effects of real
               defects in BiCMOS and Dynamic CMOS circuits, and propose
               better test solutions to detect these defects. BiCMOS and
               Dynamic CMOS circuits are used in many new high performance
               VLSI ICs.

               Fault models for BiCMOS and Dynamic CMOS circuits are
               discussed first. Shorted and open transistor terminals, the
               most common failure modes in MOS and bipolar transistors, are
               simulated for BiCMOS and Dynamic CMOS logic gates.
               Simulations show that a faulty behavior similar to data
               retention faults in memory cells can occur in BiCMOS and
               Dynamic CMOS logic gates. We explain here why it is important
               to test for these faults, and present test techniques that
               can detect these faults.

               Simulation results also show that shorts and opens in Dynamic
               CMOS and BiCMOS circuits are harder to test than their
               counterparts in Static CMOS circuits. Simulation results also
               show that the testability of opens in BiCMOS gates can be
               predicted without time-consuming transistor-level
               simulations. We present a prediction method based on an
               extended switch-level model for BiCMOS gates.

               To improve the testability of dynamic CMOS circuits,
               design-for-testability circuitry are proposed. Scan cell
               designs add scan capabilities to dynamic latches and
               flip-flops with negligible performance overhead, while
               design-for-current-testability circuitry allows quiescent
               supply current (IDDQ) measurements for dynamic CMOS circuits.
       NOTES:: [Adminitrivia V1/Prg/19950628]
         END:: STAN//CSL-TR-95-669