BIB-VERSION:: CS-TR-v2.0
          ID:: STAN//CSL-TR-94-648
       ENTRY:: December 08, 1994
ORGANIZATION:: Stanford University, Computer Systems Laboratory
       TITLE:: Automatic Synthesis of Gate-Level Speed-Independent Circuits
        TYPE:: Technical Report
      AUTHOR:: Beerel, Peter A.
      AUTHOR:: Myers, Chris J.
      AUTHOR:: Meng, Teresa H.-Y.
        DATE:: December 1994
       PAGES:: 41
    ABSTRACT:: This paper presents a CAD tool for the synthesis of robust
               asynchronous control circuits using limited-fanin basic gates
               such as AND gates, OR gates, and C-elements. The synthesized
               circuits are speed-independent; that is, they work correctly
               regardless of individual gate delays. Included in our
               synthesis procedure is an efficient procedure for logic
               optimizations using {\em observability don't cares} and {\em
               incremental verification}. We apply the procedure to a
               variety of specifications taken from industry and previously
               published examples and compare our speed-independent
               implementations to those generated using a
               non-speed-independent synthesis procedure included in
               Berkeley's SIS. Our implementations are not only more robust
               to delay variations since those produced by SIS rely on
               bounded delay lines to avoid circuit hazards but also are on
               average 13 percent faster with an area penalty of only 14
               percent.
       NOTES:: [Adminitrivia V1/Prg/19941208]
         END:: STAN//CSL-TR-94-648