BIB-VERSION:: CS-TR-v2.0
          ID:: STAN//CSL-TR-94-645
       ENTRY:: February 09, 1995
ORGANIZATION:: Stanford University, Computer Systems Laboratory
       TITLE:: Rationale, Design and Performance of the Hydra Multiprocessor
        TYPE:: Technical Report
      AUTHOR:: Olukotun, Kunle
      AUTHOR:: Bergmann, Jules
      AUTHOR:: Chang, Kun-Yung
      AUTHOR:: Nayfeh, Basem A.
        DATE:: November 1994
       PAGES:: 22
    ABSTRACT:: In Hydra four high performance processors communicate via a
               shared secondary cache. The shared cache is implemented using
               multichip module (MCM) packaging technology. The Hydra
               multiprocessor is designed to efficiently support
               automatically parallelized programs that have high degrees of
               fine grained sharing. This paper motivates the Hydra
               multiprocessor design by reviewing current trends in
               architecture and development in parallelizing compiler
               technology and implementation technology. The design of the
               Hydra multiprocessor is described and explained. Initial
               estimates of the interprocessor communication latencies show
               them to be much better than current bus-based
               multiprocessors. These lower latencies result in higher
               performance on applications with fine grained parallelism.
       NOTES:: [Adminitrivia V1/Prg/19950209]
         END:: STAN//CSL-TR-94-645