BIB-VERSION:: CS-TR-v2.0
          ID:: STAN//CSL-TR-94-643
       ENTRY:: December 20, 1994
ORGANIZATION:: Stanford University, Computer Systems Laboratory
       TITLE:: Design-for-Current-Testability (DFCT) for Dynamic CMOS Logic
        TYPE:: Technical Report
      AUTHOR:: Ma, Siyad C.
      AUTHOR:: McCluskey, Edward J.
        DATE:: November 1994
       PAGES:: 20
    ABSTRACT:: The applicability of quiescent current monitoring (IDDQ
               testing) to dynamic logic is discussed here. IDDQ is very
               useful in detecting some defects that can escape functional
               and delay tests, however, we show that some defects in domino
               logic cannot be detected by either voltage or current
               measurements. A design-for-current-testability (DFCT)
               modification for dynamic logic is presented and shown to
               enable detection of these defects. The DFCT circuitry is
               designed with a negligible performance impact during normal
               operation. This is particularly important since the main
               reason for using dynamic logic is because of its speed.
       NOTES:: [Adminitrivia V1/Prg/19941220]
         END:: STAN//CSL-TR-94-643