BIB-VERSION:: CS-TR-v2.0
          ID:: STAN//CSL-TR-94-635
       ENTRY:: September 01, 1994
ORGANIZATION:: Stanford University, Department of Computer Science
       TITLE:: A Performance/Area Workbench for Cache Memory Design
        TYPE:: Technical Report
      AUTHOR:: Okuzawa, Osamu
      AUTHOR:: Flynn, Michael J.
        DATE:: August 1994
       PAGES:: 22
    ABSTRACT:: For high performance processor design, cache memory size is
               an important parameter which directly affects performance and
               the chip area. Modeling performance and area is required for
               design tradeoff of cache memory. This paper describes a tool
               which calculates cache memory performance and area. A
               designer can try a variety of cache parameters to complete the
               specification of a cache memory. Data examples calculated
               using this tool are shown.
       NOTES:: [Adminitrivia V1/Prg/19940901]
         END:: STAN//CSL-TR-94-635