BIB-VERSION:: CS-TR-v2.0
          ID:: STAN//CSL-TR-94-630
       ENTRY:: October 27, 1994
ORGANIZATION:: Stanford University, Department of Computer Science
       TITLE:: Expansion Caches For Superscalar Processors
        TYPE:: Technical Report
      AUTHOR:: Johnson, John D.
        DATE:: June 1994
       PAGES:: 19
    ABSTRACT:: Superscalar implementations present increased demands on
               instruction caches as well as instruction decoding and
               issuing mechanisms leading to very complex hardware
               requirements. This work proposes utilizing an expanded
               instruction cache to reduce and simplify the complexity of
               hardware required to implement a superscalar machine. Trace
               driven simulation is used for evaluating the presented
               Expanded Parallel Instruction Cache (EPIC) machine and its
               performance is found to be comparable to a dynamically
               scheduled superscalar model.
       NOTES:: [Adminitrivia V1/Prg/19941027]
         END:: STAN//CSL-TR-94-630