BIB-VERSION:: CS-TR-v2.0
          ID:: STAN//CSL-TR-94-616
       ENTRY:: May 03, 1995
ORGANIZATION:: Stanford University, Computer Systems Laboratory
       TITLE:: Reuse of High Precision Arithmetic Hardware to Perform
               Multiple Low Precision Calculations
        TYPE:: Technical Report
      AUTHOR:: Zucker, Daniel
      AUTHOR:: Lee, Ruby
        DATE:: April 1994
       PAGES:: 30
    ABSTRACT:: Many increasingly important applications, such as video
               compression, graphics, or multimedia, require only
               low-precision arithmetic. However, because the widespread
               adoption of the IEEE floating point standard has led to the
               ubiquity of IEEE double precision hardware, this double
               precision hardware is frequently used to do the low precision
               calculations. Naturally, it seems an inefficient use of
               resources to use 54 bits of hardware to perform an 8 or 12
               bit calculation.

               This paper presents a method for packing operands to perform
               multiple low precision arithmetic operations using regular
               high precision hardware. Using only source level software
               modification, a speedup of 15% is illustrated for the
               Discrete Cosine Transform. Since no machine-specific
               optimizations are required, this method will work on any
               machine that supports IEEE arithmetic. Finally, an analysis
               of speedup and suggestions for future work are presented.
       NOTES:: [Adminitrivia V1/Prg/19950503]
         END:: STAN//CSL-TR-94-616