BIB-VERSION:: CS-TR-v2.0
          ID:: STAN//CSL-TR-94-614
       ENTRY:: March 21, 1994
ORGANIZATION:: Stanford University, Computer Systems Laboratory.
       TITLE:: Co-Synthesis of Hardware and Software for Digital
               Embedded Systems
        TYPE:: Thesis
        TYPE:: Technical Report
      AUTHOR:: Gupta, Rajesh Kumar
        DATE:: December 1993
       PAGES:: 282
    ABSTRACT:: As the complexity of systems being subject to computer-aided
               synthesis and optimization techniques increases, so does the
               need to find ways to incorporate predesigned components into
               the final system implementation. In this context, a
               general-purpose microprocessor provides a sophisticated
               low-cost component that can be tailored to realize most
               system functions through appropriate software. This approach
               is particularly useful in the design of embedded systems that
               have a relatively simple target architecture, when compared
               to general-purpose computing systems such as workstations. In
               embedded systems the processor is used as a resource
               dedicated to implement specific functions. However, the
               design issues in embedded systems are complicated since most
               of these systems operate in a time-constrained environment.
               Recent advances in chip-level synthesis have made it possible
               to synthesize application-specific circuits under strict
               timing constraints. This dissertation formulates the problem
               of computer-aided design of embedded systems using both
               application-specific as well as general-purpose
               reprogrammable components under timing constraints.
 
               Given a specification of system functionality and constraints
               in a hardware description language, we model the system as a
               set of bilogic flow graphs, and formulate the co-synthesis
               problem as a partitioning problem under constraints. Timing
               constraints are used to determine the parts of the system
               functionality that are delegated to application-specific
               hardware and the software that runs on the processor. The
               software component of such a 'mixed' system poses an
               interesting problem due to its interaction with concurrently
               operating hardware. We address this problem by generating
               software as a set of concurrent fixed-latency serialized
               operations called threads. The satisfaction of the imposed
               performance constraints is then ensured by exploiting
               concurrency between program threads, achieved by an
               inter-leaved execution on a single processor system.
 
               This co-synthesis of hardware and software from behavioral
               specifications makes it possible to build time-constrained
               embedded systems by using off-the-shelf parts and
               application-specific circuitry. Due to the reduction in size
               of application-specific hardware needed compared to an
               all-hardware solution, the needed hardware component can be
               easily mapped to semicustom VLSI such as gate arrays, thus
               shortening the design time. In addition, the ability to
               perform a detailed analysis of timing performance provides an
               opportunity to improve the system definition by creating
               better prototypes. The algorithms and techniques described
               have been implemented in a framework called Vulcan, which is
               integrated with the Stanford Olympus Synthesis System and
               provides a path from chip-level synthesis to system-level
               synthesis.
       NOTES:: Also published as CS-TN-94-5 by Stanford University,
               Department of Computer Science.
               [Adminitrivia V2/ACK/19940321 Changed the ID from
               CS-TN-94-5 to CSL-TR-94-614 and added Also published note.]
               [Adminitrivia V1/ACK/19940308]
         END:: STAN//CSL-TR-94-614