BIB-VERSION:: CS-TR-v2.0
          ID:: STAN//CSL-TR-94-605
       ENTRY:: March 16, 1995
ORGANIZATION:: Stanford University, Computer Systems Laboratory
       TITLE:: Performance and Area Analysis of Processor Configurations
               with Scaling of Technology
        TYPE:: Technical Report
      AUTHOR:: Fu, Steve
      AUTHOR:: Flynn, Michael J.
        DATE:: March 1994
       PAGES:: 35
    ABSTRACT:: The increasing density of transistors on integrated circuits
               and the increasing sensitivity toward costs have stimulated
               interest in developing techniques for relating transistor
               count to performance. This paper maps different processor
               configuration to transistor level area models and proposes an
               optimum evolution path of processor design as minimum feature
               size of technology is scaled. A parameter for measuring
               incremental performance improvement with respect to
               increasing transistor count is proposed.
       NOTES:: [Adminitrivia V1/Prg/19950316]
         END:: STAN//CSL-TR-94-605