BIB-VERSION:: CS-TR-v2.0
          ID:: STAN//CSL-TR-94-600
       ENTRY:: November 07, 1994
ORGANIZATION:: Stanford University, Computer Systems Laboratory
       TITLE:: Environmental Limits on the Performance of CMOS
               Wave-Pipelined Circuits
        TYPE:: Technical Report
      AUTHOR:: Nowka, Kevin J.
      AUTHOR:: Flynn, Michael J.
        DATE:: January 1994
       PAGES:: 36
    ABSTRACT:: Wave-pipelining is a circuit design technique which allows
               digital synchronous systems to be clocked at rates higher
               than can be achieved with conventional pipelining techniques.

               Wave-pipelining has been successfully applied to the design
               of SSI processor functional units, a Bipolar Population
               Counter, a CMOS adder, CMOS multipliers, and several simple
               CMOS circuits. For controlled operating environments,
               speed-ups of 2 to 10 have been reported for these designs.

               This report details the effects of temperature variation,
               supply voltage variation, and process variation on
               wave-pipelined static CMOS designs, derives limits for the
               performance of wave-pipelined circuits due to these
               variations, and compares the performance effects with those
               of traditional pipelined circuits.

               This study finds that wave-pipelined circuits designed for
               commercial operating environments are limited to 2 to 3 waves
               per pipeline stage when clocked from a fixed frequency
               source. Variable rate, internal clocking can approach the
               theoretical limit of waves at a cost of interface complexity.
       NOTES:: [Adminitrivia V1/Prg/19941107]
         END:: STAN//CSL-TR-94-600