BIB-VERSION:: CS-TR-v2.0
          ID:: STAN//CSL-TR-93-591
       ENTRY:: November 17, 1994
ORGANIZATION:: Stanford University, Computer Systems Laboratory
       TITLE:: Logic Synthesis for Concurrent Error Detection
        TYPE:: Technical Report
      AUTHOR:: Touba, Nur A.
      AUTHOR:: McCluskey, Edward J.
        DATE:: November 1993
       PAGES:: 32
    ABSTRACT:: The structure of a circuit determines how the effects of a
               fault can propagate and hence affects the cost of concurrent
               error detection. By considering circuit structure during
               logic optimization, the overall cost of a concurrently
               checked circuit can be minimized. This report presents a new
               technique called structure-constrained logic optimization
               (SCLO) that optimizes a circuit under the constraint that
               faults in the resulting circuit can produce only a prescribed
               set of errors. Using SCLO, circuits can be optimized for
               various concurrent error detection schemes allowing the
               overall cost for each scheme to be compared. A technique for
               quickly estimating the size of a circuit under different
               structural constraints is described. This technique enables
               rapid exploration of the design space for concurrently
               checked circuits. A new method for the automated synthesis of
               self-checking circuit implementations for arbitrary
               combinational circuits is also presented. It consists of an
               algorithm that determines the best parity-check code for
               encoding the output of a given circuit, and then uses SCLO to
               produce the functional circuit which is augmented with a
               checker to form a self-checking circuit. This synthesis
               method provides fully automated design, explores a larger
               design space than other methods, and uses simple checkers. It
               has been implemented by making modifications to SIS (an
               updated version of MIS [Brayton 87a]), and results for
               several MCNC combinational benchmark circuits are given. In
               most cases, a substantial reduction in overhead compared to a
               duplicate-and-compare implementation is achieved.
       NOTES:: [Adminitrivia V1/Prg/19941117]
         END:: STAN//CSL-TR-93-591