BIB-VERSION:: CS-TR-v2.0
          ID:: STAN//CSL-TR-93-584
       ENTRY:: November 07, 1994
ORGANIZATION:: Stanford University, Computer Systems Laboratory
       TITLE:: Optimization of Combinational Logic Circuits Based on
               Compatible Gates
        TYPE:: Technical Report
      AUTHOR:: Damiani, Maurizio
      AUTHOR:: Yang, Jerry Chih-Yuan
      AUTHOR:: DeMicheli, Giovanni
        DATE:: June 1993
       PAGES:: 30
    ABSTRACT:: This paper presents a set of new techniques for the
               optimization of multiple-level combinational Boolean
               networks. We describe first a technique based upon the
               selection of appropriate "multiple-output" subnetworks
               (consisting of so-called "compatible gates" whose local
               functions can be optimized simultaneously. We then generalize
               the method to larger and more arbitrary subsets of gates.
               Because simultaneous optimization of local functions can take
               place, our methods are more powerful and general than Boolean
               optimization methods using "don't cares", where only
               single-gate optimization can be performed. In addition, our
               methods represent a more efficient alternative to
               optimization procedures based on Boolean relations because
               the problem can be modeled by a "unate" covering problem
               instead of the more difficult "binate" covering problem. The
               method is implemented in program ACHILLES and compares
               favorably to SIS .
       NOTES:: [Adminitrivia V1/Prg/19941107]
         END:: STAN//CSL-TR-93-584