BIB-VERSION:: CS-TR-v2.0
          ID:: STAN//CSL-TR-93-580
       ENTRY:: November 09, 1994
ORGANIZATION:: Stanford University, Computer Systems Laboratory
       TITLE:: Automatic Technology Mapping for Generalized Fundamental-Mode
               Asynchronous Designs
        TYPE:: Technical Report
      AUTHOR:: Siegel, Polly
      AUTHOR:: DeMicheli, Giovanni
      AUTHOR:: Dill, David
        DATE:: June 1993
       PAGES:: 31
    ABSTRACT:: The generalized fundamental-mode asynchronous design style is
               one in which the combinational portions of the circuit design
               are separated from the storage elements, as with synchronous
               design styles. Synchronous technology mapping techniques can
               be adapted to work for this asynchronous design style if
               hazards are taken into account. First, we examine each step
               of algorithmic technology mapping for its influence on the
               hazard behavior of the modified network. We then present
               modifications to an existing synchronous technology mapper to
               work for this asynchronous design style. We present efficient
               algorithms for hazard analysis that are used during the
               mapping process. These algorithms have been implemented and
               incorporated into the program CERES to produce a technology
               mapper suitable for asynchronous designs.
       NOTES:: [Adminitrivia V1/Prg/19941109]
         END:: STAN//CSL-TR-93-580