BIB-VERSION:: CS-TR-v2.0
          ID:: STAN//CSL-TR-92-523
       ENTRY:: November 02, 1994
ORGANIZATION:: Stanford University, Computer Systems Laboratory
       TITLE:: ARCHITECTURAL AND IMPLEMENTATION TRADEOFFS IN THE DESIGN OF
               MULTIPLE-CONTEXT PROCESSORS
        TYPE:: Technical Report
      AUTHOR:: Laudon, James
      AUTHOR:: Gupta, Anoop
      AUTHOR:: Horowitz, Mark
        DATE:: May 1992
       PAGES:: 27
    ABSTRACT:: Multiple-context processors have been proposed as an
               architectural technique to mitigate the effects of large
               memory latency in multiprocessors. We examine two schemes for
               implementing multiple-context processors. The first scheme
               switches between contexts only on a cache miss, while the
               other interleaves the contexts on a cycle-by-cycle basis.
               Both schemes provide the capability for a single context to
               fully utilize the pipeline. We show that cycle-by-cycle
               interleaving of contexts provides a performance advantage
               over switching contexts only at a cache miss. This advantage
               results from the context interleaving hiding pipeline
               dependencies and reducing the context switch cost. In
               addition, we show that while the implementation of the
               interleaved scheme is more complex, the complexity is not
               overwhelming. As pipelines get deeper and operate at lower
               percentages of peak performance, the performance advantage of
               the interleaved scheme is likely to justify its additional
               complexity.
       NOTES:: [Adminitrivia V1/Prg/19941102]
         END:: STAN//CSL-TR-92-523