BIB-VERSION:: CS-TR-v2.0
          ID:: STAN//CSL-TR-91-468
       ENTRY:: November 08, 1994
ORGANIZATION:: Stanford University, Computer Systems Laboratory
       TITLE:: EFFICIENT MOMENT-BASED TIMING ANALYSIS FOR VARIABLE ACCURACY
               SWITCH LEVEL SIMULATION
        TYPE:: Technical Report
      AUTHOR:: Kao, Russell
      AUTHOR:: Horowitz, Mark
        DATE:: April 1991
       PAGES:: 19
    ABSTRACT:: We describe a timing analysis algorithm which can achieve the
               efficiency of RC tree analysis while retaining much of the
               generality of Asymptotic Waveform Estimation. RC tree
               analysis from switch level simulation is generalized to
               handle piecewise linear transistor models, non tree
               topologies, floating capacitors, and feedback. For simple
               switch level models the complexity is O(n). The algorithm
               allows the user to trade off efficiency vs accuracy through
               the selection of transistor models of varying complexity.
       NOTES:: [Adminitrivia V1/Prg/19941108]
         END:: STAN//CSL-TR-91-468