BIB-VERSION:: CS-TR-v2.0
          ID:: STAN//CSL-TR-87-326
       ENTRY:: November 08, 1994
ORGANIZATION:: Stanford University, Computer Systems Laboratory
       TITLE:: SRT DIVISION DIAGRAMS AND THEIR USAGE IN DESIGNING INTEGRATED
               CIRCUITS FOR DIVISION
        TYPE:: Technical Report
      AUTHOR:: Williams, Ted E.
      AUTHOR:: Horowitz, Mark
        DATE:: November 1986
       PAGES:: 24
    ABSTRACT:: This paper describes the construction and analysis of several
               diagrams which depict SRT division algorithms. These diagrams
               yield insight into the operation of the algorithms and the
               many implementation tradeoffs available in custom circuit
               design. Examples of simple low radix diagrams are shown, as
               well as tables for higher radices. The tables were generated
               by a program which can create and verify the diagrams for
               different division schemes. Also discussed is a custom CMOS
               integrated circuit designed which performs SRT division using
               self-timed circuit techniques. This chip implements an
               intermediate approach between a fully combinational array and
               a fully iterative in time method in order to get both speed
               and small silicon area.
       NOTES:: [Adminitrivia V1/Prg/19941108]
         END:: STAN//CSL-TR-87-326