BIB-VERSION:: CS-TR-v2.0
          ID:: STAN//CSL-TR-86-303
       ENTRY:: November 08, 1994
ORGANIZATION:: Stanford University, Computer Systems Laboratory
       TITLE:: THE SEMANTICS OF TIMING CONSTRUCTS IN HARDWARE DESCRIPTION
               LANGUAGES
        TYPE:: Technical Report
      AUTHOR:: Luckham, David C.
      AUTHOR:: Huh, Youm
      AUTHOR:: Stanculescu, Alec G.
        DATE:: August 1986
       PAGES:: 31
    ABSTRACT:: Three different approaches to the representation of time in
               high level hardware design languages are described and
               compared. The first is the timed assignment statement of
               ADLIB/SABLE which anticipates future events. The second is
               the timed assignment of VHDL which predicts future events and
               allows predictions to be preempted by other predictions. The
               third is a new proposed method of expressing time dependency
               by qualifying expressions so that their values are required
               to be constant over a specified time interval. Examples
               comparing these three approaches are given. It is shown how
               time-qualified expressions could be introduced into a
               hardware description language. The possibility of proving
               correctness of hardware models in this language is
               illustrated.
       NOTES:: [Adminitrivia V1/Prg/19941108]
         END:: STAN//CSL-TR-86-303