BIB-VERSION:: CS-TR-v2.0
          ID:: STAN//CSL-TR-83-236
       ENTRY:: December 01, 1994
ORGANIZATION:: Stanford University, Computer Systems Laboratory
       TITLE:: DESIGN OF A HIGH PERFORMANCE VLSI PROCESSOR
        TYPE:: Technical Report
      AUTHOR:: Hennessy, John L.
      AUTHOR:: Jouppi, Norman
      AUTHOR:: Przybylski, Steven
      AUTHOR:: Rowen, Christopher
      AUTHOR:: Gross, Thomas
        DATE:: February 1983
       PAGES:: 27
    ABSTRACT:: Current VLSI fabrication technology makes it possible to
               design a 32-bit CPU on a single chip. However, to achieve
               high performance from that processor, the architecture and
               implementation must be carefully designed and tuned. The MIPS
               processor incorporates some new architectural ideas into a
               single-chip, nMOS implementation. Processor performance is
               obtained by the careful integration of the software (e.g.,
               compilers), the architecture, and the hardware
               implementation. This integrated view also simplifies the
               design, making it practical to implement the processor at a
               university.
       NOTES:: [Adminitrivia V1/Prg/19941201]
         END:: STAN//CSL-TR-83-236