BIB-VERSION:: CS-TR-v2.0
          ID:: STAN//CSL-TR-81-223
       ENTRY:: December 01, 1994
ORGANIZATION:: Stanford University, Computer Systems Laboratory
       TITLE:: MIPS: A VLSI PROCESSOR ARCHITECTURE
        TYPE:: Technical Report
      AUTHOR:: Hennessy, John L.
      AUTHOR:: Jouppi, Norman
      AUTHOR:: Baskett, Forest
      AUTHOR:: Gill, John
        DATE:: November 1981
       PAGES:: 12
    ABSTRACT:: MIPS is a new single chip VLSI processor architecture. It
               attempts to achieve high performance with the use of a
               simplified instruction set, similar to those found in
               microengines. The processor is a fast pipelined engine
               without pipeline interlocks. Software solutions to several
               traditional hardware problems, such as providing pipeline
               interlocks, are used.
       NOTES:: [Adminitrivia V1/Prg/19941201]
         END:: STAN//CSL-TR-81-223