BIB-VERSION:: CS-TR-v2.0
          ID:: STAN//CSL-TR-77-142
       ENTRY:: December 01, 1994
ORGANIZATION:: Stanford University, Computer Systems Laboratory
       TITLE:: OPTIMAL LAYOUT OF CMOS FUNCTIONAL ARRAYS
        TYPE:: Technical Report
      AUTHOR:: Uehara, T.
      AUTHOR:: vanCleemput, Willem M.
        DATE:: March 1978
       PAGES:: 41
    ABSTRACT:: Designers of MOS LSI circuits can take advantage of complex
               functional cells in order to achieve better performance. This
               paper discusses the implementation of a random logic function
               on an array of CMOS transistors. A graph-theoretical
               algorithm which minimizes the size of an array is presented.
               This method is useful for the design of cells used in
               conventional design automation systems.
       NOTES:: [Adminitrivia V1/Prg/19941201]
         END:: STAN//CSL-TR-77-142