BIB-VERSION:: CS-TR-v2.0
          ID:: STAN//CSL-TR-75-102
       ENTRY:: December 01, 1994
ORGANIZATION:: Stanford University, Computer Systems Laboratory
       TITLE:: HIGH PERFORMANCE EMULATION
        TYPE:: Technical Report
      AUTHOR:: Wallach, Walter A. Jr.
        DATE:: November 1975
       PAGES:: 17
    ABSTRACT:: The Stanford EMMY is examined as an emulation engine. Using
               the 360 emulator and the DELtran interpreter as examples, the
               performance of the current EMMY architecture is examined as a
               high performance emulation vehicle. The problems of using a
               sequential, vertically organized processor for high speed
               emulation are developed and discussed.

               A flexible control structure for high speed emulation studies
               is derived from an existing high performance processor. This
               structure issues a stream of microinstructions to a central
               command bus, allowing user-defined execution resources to
               execute them in overlapped fashion. These execution resources
               may be added or deleted with little or no processor rewiring.
       NOTES:: [Adminitrivia V1/Prg/19941201]
         END:: STAN//CSL-TR-75-102