Report Number: CSL-TR-99-783
Institution: Stanford University, Computer Systems Laboratory
Title: Optimum Instruction-level Parallelism (ILP) for Superscalar
and VLIW Processors
Author: Hung, Patrick
Author: Flynn, Michael J.
Date: July 1999
Abstract: Modern superscalar and VLIW processors fetch, decode,
issue, execute, and retire multiple instructions per
cycle. By taking advantage of instruction-level
parallelism (ILP), processor performance can be
improved substantially. However, increasing the level
of ILP may eventually result in diminishing and
negative returns due to control and data dependencies
among subsequent instructions as well as resource
conflicts within a processor. Moreover, the
additional ILP complexity can have significant
overload in cycle time and latency.
This technical report uses a generic processor
model to investigate the optimum level of ILP
for superscalar and VLIW processors.