Report Number: CSL-TR-98-772
Institution: Stanford University, Computer Systems Laboratory
Title: Designing a Partitionable Multiplier
Author: Lee, Hyuk-Jun
Author: Flynn, Michael
Date: October 1998
Abstract: This report presents the design of a 64-bit integer multiplier core that can perform 32-bit or 16-bit parallel integer multiplications(PMUL) and 32-bit or 16-bit parallel integer multiplications followed by additions(PMADD). The proposed multiplier removes sign and constant bits from its core and projects them to the boundaries to minimize the complexity of base cells. It also adopts an array-of-arrays architecture with unequal array sizes by decoupling partial product generation from carry save addition. This makes it possible to achieve high speed for 64-bit multiplication. Two architectures, which are done in dual-rail domino, are tested for functionality in Verilog and simulated in HSPICE for TSMC 0.35um process. The first architecture is capable of both PMUL and PMADD. The estimated delay is 4.9 ns (excluding a final adder) at 3.3V supply and 25c and its estimated area is 6.5 mm*2. The estimated delay of the second architecture, only capable of PMUL, is 4.5 ns. Its estimated area is 5.2 mm*2.