Report Number: CSL-TR-97-748
Institution: Stanford University, Computer Systems Laboratory
Title: Decision Diagrams and Pass Transistor Logic Synthesis
Author: Bertacco, V.
Author: Minato, S.
Author: Verplaetse, P.
Author: Benini, L.
Author: Micheli, and G. De
Date: December 1997
Abstract: Since the relative importance of interconnections increases as feature size decreases, standard-cell based synthesis becomes less effective when deep-submicron technologies become available. Intra-cell connectivity can be decreased by the use of macro-cells. In this work we present methods for the automatic generation of macro-cells using pass transistors and domino logic. The synthesis of these cells is based on BDD and Z BDD representations of the logic functions. We address specific problems associated with the BDD approach (level degradation, long paths) and the Z BDD approach (sneak paths, charge sharing, long paths). We compare performance of the macro-cells approach versus the conventional standard-cell approach based on accurate electrical simulation. This shows that the macro-cells perform well up to a certain complexity of the logic function. Functions of high complexity must be decomposed into smaller logic blocks that can directly be mapped to macro-cells.