Report Number: CSL-TR-97-739
Institution: Stanford University, Computer Systems Laboratory
Title: Hardware/Software Co-Design of Run-Time Schedulers for
Author: Mooney, Vincent John III
Author: Micheli, Giovanni De
Date: November 1997
Abstract: We present the SERRA Run-Time Scheduler Synthesis and
Analysis Tool which automatically generates a run-time
scheduler from a heterogeneous system-level specification in
both Verilog HDL and C. Part of the run-time scheduler is
implemented in hardware, which allows the scheduler to be
predictable in being able to meet hard real-time constraints,
while part is implemented in software, thus supporting
features typical of software schedulers.
SERRA's real-time analysis generates a priority assignment
for the software tasks in the mixed hardware-software system.
The tasks in hardware and software have precedence
constraints, resource constraints, relative timing
constraints, and a rate constraint. A heuristic scheduling
algorithm assigns the static priorities such that a hard
real-time rate constraint can be predictably met. SERRA
supports the specification of critical regions in software,
thus providing the same functionality as semaphores.
We describe the task control/data-flow extraction, synthesis
of the control portion of the run-time scheduler in hardware,
real-time analysis and priority scheduler template. We also
show how our approach fits into an overall tool flow and
target architecture. Finally, we conclude with a sample
application of the novel run-time scheduler synthesis and
analysis tool to a robotics design example.