Report Number: CSL-TR-97-715
Institution: Stanford University, Computer Systems Laboratory
Title: Software and Hardware for Exploiting Speculative Parallelism with a Multiprocessor
Author: Oplinger, Jeffrey
Author: Heine, David
Author: Liao, Shih-Wei
Author: Nayfeh, Basem A.
Author: Lam, Monica S.
Author: Olukotun, Kunle
Date: february 1997
Abstract: Thread-level speculation (TLS) makes it possible to parallelize general purpose C programs. This paper proposes software and hardware mechanisms that support speculative thread- level execution on a single-chip multiprocessor. A detailed analysis of programs using the TLS execution model shows a bound on the performance of a TLS machine that is promising. In particular, TLS makes it feasible to find speculative do across parallelism in outer loops that can greatly improve the performance of general-purpose applications. Exploiting speculative thread-level parallelism on a multiprocessor requires the compiler to determine where to speculate, and to generate SPMD (single program multiple data) code.We have developed a fully automatic compiler system that uses profile information to determine the best loops to execute speculatively, and to generate the synchronization code that improves the performance of speculative execution. The hardware mechanisms required to support speculation are simple extensions to the cache hierarchy of a single chip multiprocessor. We show that with our proposed mechanisms, thread-level speculation provides significant performance benefits.