Report Number: CSL-TR-96-707
Institution: Stanford University, Computer Systems Laboratory
Title: Reducing Cache Miss Rates Using Prediction Caches
Author: Bennett, James E.
Author: Flynn, Michael J.
Date: October 1996
Abstract: Processor cycle times are currently much faster than memory cycle times, and the trend has been for this gap to increase over time. The problem of increasing memory latency, relative to processor speed, has been dealt with by adding high speed cache memory. However, it is difficult to make a cache both large and fast, so that cache misses are expected to continue to have a significant performance impact. Prediction caches use a history of recent cache misses to predict future misses, and to reduce the overall cache miss rate. This paper describes several prediction caches, and introduces a new kind of prediction cache, which combines the features of prefetching and victim caching. This new cache is shown to be more effective at reducing miss rate and improving performance than existing prediction caches.
http://i.stanford.edu/pub/cstr/reports/csl/tr/96/707/CSL-TR-96-707.pdf