Report Number: CSL-TR-95-672
Institution: Stanford University, Computer Systems Laboratory
Title: Delay Models for CMOS Circuits
Author: McFarland, Grant
Author: Flynn, Michael
Date: June 1995
Abstract: Four different CMOS inverter delay models are derived and compared. It is shown that inverter delay can be estimated with fair accuracy over a wide range of input rise times and loads as the sum of two terms, one proportional to the input rise time, and one proportional to the capacitive load. Methods for estimating device capacitance from HSPICE parameters are presented, as well as means of including added delay due to wire resistance and the use of series transistors.