Report Number: CSL-TR-95-671
Institution: Stanford University, Computer Systems Laboratory
Title: Characterization and reduction of metastability errors in CMOS interface circuits
Author: Portmann, Clemenz Lenard
Date: June 1995
Abstract: In synchronous digital logic systems, asynchronous external
signals must be referenced to the system clock or
synchronized. Synchronization of asynchronous signals,
however, inevitably leads to metastability errors.
Metastability error rates can increase by orders of magnitude
as clock frequencies increase in high performance designs,
and supply voltages decrease in low- power designs. This
research focuses on the characterization of metastability
parameters and error reduction with no penalty in circuit
performance. Two applications, high-speed flash analog-
to-digital conversion and synchronization of asynchronous
binary signals in application-specific integrated circuits
have been investigated.
Applications such as telecommunications and instrumentation
for time-domain analysis require analog-to-digital converters
with metastability error probabilities on the order of 10^-10
errors/ cycle, achievable in high performance designs only
through the use of dedicated circuitry for error reduction. A
power and area efficient externally pipelined metastability
error reduction technique for flash converters has been
developed. Unresolved comparator outputs are held valid,
causing the encode logic to fail benignly in the presence of
metastability. In an n bit converter, errors are passed as a
single unsettled bit to the converter output and are reduced
with an external pipeline of only n latches per stage rather
than an internal pipeline of 2^n-1 latches per stage.
An 80-MHz, externally pipelined, 7-bit flash
analog-to-digital converter was fabricated in 1.2-um CMOS.
Measured error rates were less than 10^-12 errors/cycle.
Using internal pipelining with two levels of 127 latches to
achieve equivalent performance would require 3.48 times more
power for the error reduction circuitry with a Nyquist
frequency input. This corresponds to a reduction in the total
power for the implemented converter of 1.24 times compared
with the internally pipelined converter.
In synchronizers and arbiters, general purpose applications
require mean time between failures on the order of one per
year or tens of years. Comparison of previous designs has
been difficult due to varying technologies, test setups, and
test conditions. To address this problem, a test circuit for
synchronizers was implemented in 2-um and 1.2-um CMOS
technologies. Using the test setup, the evaluation and
comparison of synchronizer performance in varying
environments and technologies is possible. The effects of
loading, output buffering, supply scaling, supply noise, and
technology scaling on synchronizer performance are discussed.