Report Number: CSL-TR-95-662
Institution: Stanford University, Computer Systems Laboratory
Title: Limits of Scaling MOSFETs
Author: McFarland, Grant
Author: Flynn, Michael J.
Date: January 1995
Abstract: The fundamental electrical limits of MOSFETs are discussed
and modeled to predict the scaling limits of digital bulk
CMOS circuits. Limits discussed include subthreshold
currents, time dependent dielectric breakdown (TDDB), hot
electron effects, and drain induced barrier lowering (DIBL).
This paper predicts the scaling of bulk CMOS MOSFETs to reach
its limits at drawn dimensions of approximately 0.1um. These
electrical limits are used to find scaling factors for SPICE
Level 3 model parameters, and a scalable Level 3 device model
is presented. Current trends in scaling interconnects are