Report Number: CSL-TR-95-661
Institution: Stanford University, Computer Systems Laboratory
Title: Performance Factors for Superscalar Processors
Author: Bennett, James E.
Author: Flynn, Michael J.
Date: February 1995
Abstract: This paper introduces three performance factors for
dynamically scheduled superscalar processors. These factors,
availability, efficiency, and utility, are then used to
explain the variations in performance that occur with
different processor and memory system features. The processor
features that are investigated are branch prediction depth
and following multiple branch paths. The memory system
features that are investigated are cache size, associativity,
miss penalty, and memory bus bandwidth. Dynamic scheduling
with appropriate levels of bus bandwidth and branch
prediction is shown to be remarkably effective at achieving
good performance over a range of differing application types
and over a range of cache miss rates. These results were
obtained using a new simulation environment, MXS, which
directly executes the benchmarks.