Report Number: CSL-TR-94-645
Institution: Stanford University, Computer Systems Laboratory
Title: Rationale, Design and Performance of the Hydra Multiprocessor
Author: Olukotun, Kunle
Author: Bergmann, Jules
Author: Chang, Kun-Yung
Author: Nayfeh, Basem A.
Date: November 1994
Abstract: In Hydra four high performance processors communicate via a shared secondary cache. The shared cache is implemented using multichip module (MCM) packaging technology. The Hydra multiprocessor is designed to efficiently support automatically parallelized programs that have high degrees of fine grained sharing. This paper motivates the Hydra multiprocessor design by reviewing current trends in architecture and development in parallelizing compiler technology and implementation technology. The design of the Hydra multiprocessor is described and explained. Initial estimates of the interprocessor communication latencies show them to be much better than current bus-based multiprocessors. These lower latencies result in higher performance on applications with fine grained parallelism.