Report Number: CSL-TR-94-643
Institution: Stanford University, Computer Systems Laboratory
Title: Design-for-Current-Testability (DFCT) for Dynamic CMOS Logic
Author: Ma, Siyad C.
Author: McCluskey, Edward J.
Date: November 1994
Abstract: The applicability of quiescent current monitoring (IDDQ
testing) to dynamic logic is discussed here. IDDQ is very
useful in detecting some defects that can escape functional
and delay tests, however, we show that some defects in domino
logic cannot be detected by either voltage or current
measurements. A design-for-current-testability (DFCT)
modification for dynamic logic is presented and shown to
enable detection of these defects. The DFCT circuitry is
designed with a negligible performance impact during normal
operation. This is particularly important since the main
reason for using dynamic logic is because of its speed.