Report Number: CSL-TR-94-635
Institution: Stanford University, Department of Computer Science
Title: A Performance/Area Workbench for Cache Memory Design
Author: Okuzawa, Osamu
Author: Flynn, Michael J.
Date: August 1994
Abstract: For high performance processor design, cache memory size is
an important parameter which directly affects performance and
the chip area. Modeling performance and area is required for
design tradeoff of cache memory. This paper describes a tool
which calculates cache memory performance and area. A
designer can try a variety of cache parameters to complete the
specification of a cache memory. Data examples calculated
using this tool are shown.