Report Number: CSL-TR-94-630
Institution: Stanford University, Department of Computer Science
Title: Expansion Caches For Superscalar Processors
Author: Johnson, John D.
Date: June 1994
Abstract: Superscalar implementations present increased demands on
instruction caches as well as instruction decoding and
issuing mechanisms leading to very complex hardware
requirements. This work proposes utilizing an expanded
instruction cache to reduce and simplify the complexity of
hardware required to implement a superscalar machine. Trace
driven simulation is used for evaluating the presented
Expanded Parallel Instruction Cache (EPIC) machine and its
performance is found to be comparable to a dynamically
scheduled superscalar model.