Report Number: CSL-TR-94-625
Institution: Stanford University, Computer Systems Laboratory
Title: An Experimental Chip to Evaluate Test Techniques Part 1:
Description of Experiment
Author: Franco, Piero
Author: Stokes, Robert L.
Author: Farwell, William D.
Author: McCluskey, Edward J.
Date: June 1994
Abstract: A Test Chip has been designed and manufactured to evaluate
different testing techniques for combinational or full-scan
circuits. The Test Chip is a 25k gate CMOS gate-array using
LSI Logic's LFT150K technology, and includes support (design
for testability) circuitry and five types of
circuits-under-test (CUT). Over 5,000 die have been
The five circuits-under-test include both datapath and
synthesized control logic. The tests include design
verification (simulation), exhaustive, pseudo-random, and
deterministic vectors for various fault models (stuck-at,
transition, delay faults, and IDDQ Testing). The chip will
also be testing using the CrossCheck methodology, as well as
other new technques, including Stability Checking and
Very-Low-Voltage Testing. The experiment includes an
investigation of both serial and parallel signature analysis.
This report describes the Test Evaluation Chip Experiment,
including the design of the Test Chip and the tests applied.
A future report will cover the experimental results and data