Report Number: CSL-TR-94-621
Institution: Stanford University, Computer Systems Laboratory
Title: Synthesis for Scan Dependence in Built-In Self-Testable
Author: Avra, LaNae J.
Author: McCluskey, Edward J.
Date: May 1994
Abstract: This report introduces new design and synthesis techniques
that reduce the area and improve the performance of embedded
built-in self-test (BIST) architectures such as circular BIST
and parallel BIST. Our goal is to arrange the system
bistables into scan paths so that some of the BIST and scan
logic is shared with the system logic. Logic sharing is
possible when scan dependence is introduced in the design.
Other BIST design techniques attempt to avoid all types of
scan dependence because it can reduce the fault coverage of
embedded, multiple input signature registers (MISRs). We show
that introducing certain types of scan dependence in embedded
MISRs can result in reduced overhead and improved fault
coverage, and we describe synthesis techniques that maximize
the amount of this beneficial scan dependence. Finally, we
present fault simulation, layout area, and delay results for
circular BIST versions of benchmark circuits that have been
synthesized with our techniques.